International Journal of Reconfigurable Computing

On a Real-Time Blind Signal Separation Noise Reduction System

Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL

Corrigendum to “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization”

Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator

Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

RP-Ring: A Heterogeneous Multi-FPGA Accelerator

Corrigendum to “Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm”

Corrigendum to “PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability”

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

International Journal of Reconfigurable Computing

Table of Contents

Table of Contents: 2018

On a Real-Time Blind Signal Separation Noise Reduction System

Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL

Corrigendum to “An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization”

Exploiting Partial Reconfiguration through PCIe for a Microphone Array Network Emulator

Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction

RP-Ring: A Heterogeneous Multi-FPGA Accelerator

Corrigendum to “Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm”

Corrigendum to “PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability”

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method