International Journal of Reconfigurable Computing

Current Trends on Reconfigurable Computing

Selected Papers from SPL 2008: Programmable Logic and Applications

Neuromorphic Configurable Architecture for Robust Motion Estimation

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration

Burst-Mode Asynchronous Controllers on FPGA

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System

On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Dynamic Hardware Development

SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC

FPGA-Based Embedded Motion Estimation Sensor

International Journal of Reconfigurable Computing

Table of Contents

Table of Contents: 2008

Current Trends on Reconfigurable Computing

Selected Papers from SPL 2008: Programmable Logic and Applications

Neuromorphic Configurable Architecture for Robust Motion Estimation

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration

Burst-Mode Asynchronous Controllers on FPGA

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology

Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System

On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation

An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture

Dynamic Hardware Development

SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC

FPGA-Based Embedded Motion Estimation Sensor