International Journal of Reconfigurable Computing

SIFO: Secure Computational Infrastructure Using FPGA Overlays

From FPGA to Support Cloud to Cloud of FPGA: State of the Art

Automatic Pipelining and Vectorization of Scientific Code for FPGAs

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

Implementing and Evaluating an Heterogeneous, Scalable, Tridiagonal Linear System Solver with OpenCL to Target FPGAs, GPUs, and CPUs

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

Exposing End-to-End Delay in Software-Defined Networking

AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

International Journal of Reconfigurable Computing

Table of Contents

Table of Contents: 2019

SIFO: Secure Computational Infrastructure Using FPGA Overlays

From FPGA to Support Cloud to Cloud of FPGA: State of the Art

Automatic Pipelining and Vectorization of Scientific Code for FPGAs

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick

Implementing and Evaluating an Heterogeneous, Scalable, Tridiagonal Linear System Solver with OpenCL to Target FPGAs, GPUs, and CPUs

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

Exposing End-to-End Delay in Software-Defined Networking

AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation