International Journal of Reconfigurable Computing

Open SystemC Simulator with Support for Power Gating Design

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures

Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic

A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme

HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs

A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication

Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation

Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)

Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders

Modeling and Implementation of a Power Estimation Methodology for SystemC

International Journal of Reconfigurable Computing

Table of Contents

Table of Contents: 2012

Open SystemC Simulator with Support for Power Gating Design

Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems

High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures

Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic

A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme

HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs

A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication

Multidimensional Costas Arrays and Their Enumeration Using GPUs and FPGAs

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs

DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation

Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)

Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders

Modeling and Implementation of a Power Estimation Methodology for SystemC