In this paper we present a new tool for the encoding of multi-level finite state machines based on the concept ofevolution programming. Evolution programs are stochastic adaptive algorithms, based on the paradigm of geneticalgorithms whose search methods model some natural phenomenon: genetic inheritance and Darwinian strife forsurvival. Crossover and mutation rates were tailored to the state assignment problem experimentally. We presentresults over a wide range of MCNC benchmarks which demonstrate the effectiveness of the new tool. The resultsshow that evolution programs can be effectively applied to state assignment.

S.  Muddappa

R. Z. Makki

Z.  Michalewicz

S.  Isukapalli

Pioneer: A New Tool for Coding of Multi-Level FiniteState Machines Based on Evolution Programming

In this paper, we address the technology mapping for RAM-based FPGA. Functional decomposition is appliedto decompose a large function into a set of smaller subfunctions such that each subfunction can be implementedusing a single logic cell. Our system is mainly divided into two parts. The first part is designed specifically fortotally symmetric functions. A Fast-Decompose algorithm based on weight dependency is proposed. The secondpart deals with general functions. We consider some techniques such as output partition, variable partition, don&#39;tcare assignment and encoding to minimize the number of subfunctions derived. Using these techniques together,our tool, Fun-Map, improves the mapping results compared with other tools in terms of area and delay.

Kuo-Hua  Wang

Cheng  Chen

Ting Ting Hwang

Technology Mapping for FPGA Using GeneralizedFunctional Decomposition

Si-Qing  Zheng

Dian  Zhou

Preface

In this paper, we study the problem of state assignment as it relates to silicon area, propagation delay time and
testability of finite state machines. The results of a study involving various FSM benchmarks show that the simple
technique of one-hot encoding often produces better results than those attained by complex state assignment
algorithms.

S. Su

Analysis and Characterization of State Assignment
Techniques for Sequential Machines

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises becauseof reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits.Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. Ahierarchical test generation algorithm is proposed.

Anand V. Hudli

Raghu V. Hudli

Temporal Logic Based Hierarchical Test Generationfor Sequential VLSI Circuits

The use of programmable logic cells in VLSI design allows the terminals on these cells to be interchanged sincetheir geometrics are programmable. Recently, many exact algorithms and heuristics have been proposed forchannel routing with interchangeable terminals [18, 25, 4, 11, 12, 20, 17, 3]. Various optimization problems havealso been shown to be NP&#8212;hard [25, 23]. In this paper, we consider channels with exits. Let m, D be the numberof terminals in the channel and the maximum number of terminals on a net, respectively. We present an O(m)algorithm that obtains optimal density for channels with exits that have one cell on each side. The existingalgorithm for this problem [5] guarantees only an approximate density. Moreover, if one of the two cells hasfixed terminals, we show that the density minimization problem is NP-hard. The latter problem was introducedin [5]. For instances with any number of cells we present an O(m) time algorithm for the via minimization problem,an O(<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msup><mml:mi>m</mml:mi><mml:mn>2</mml:mn></mml:msup><mml:mo>&#x22C5;</mml:mo><mml:mi>D</mml:mi></mml:mrow></mml:math>) algorithm for the problem of finding a maximum planar subset of nets in a channel, and an O(m)algorithm to determine whether the channel adopts external-internal layout. Also for the special case where thereexists one cell per side, we present an alternative algorithm that finds a maximum planar set of nets in O(m)time.

Spyros  Tragoudas

On Channel Routing Problems WithInterchangeable Terminals

Redesigning the LFSR (Linear Feedback Shift Register) so that syndrome calculations can be performed in onesweep allows for fast error control in high speed computer networks. The resulting structure forms the basis ofthe PEDDC (Parallel Encoder, Decoder, Detector, Corrector) which replaces the conventional Serial Encoder,Decoder, Detector, Corrector for generation and utilization of cyclic codes. Since syndromes are calculated inas little as one clock period, information from which the syndrome is calculated can be processed in a parallelstream. In this paper a simple PEDDC is built, its operation is examined in detail, its performance is comparedwith a serial counterpart, possible variations on the PEDDC structure is given, and further speed enhancementtechniques are considered.

Andrzej  Sobski

Alexander  Albicki

High Throughput Error Control Using Parallel CRC

While the performance, density, and complexity of application-specific systems increase at a rapid pace, equivalent
advances are not being made in making them more easily testable, diagnosable, and maintainable. Even though
testability bus standards, like JTAG Boundary Scan, have been developed to help eliminate these costs, there
exists a need for efficient hardware and software tools to support them. Hence, a testability design and hardware
support environment for application-specific systems is described which provides a designer with a set of hardware
modules and circuitry, that support these standards and software tools for automatic incorporation of testability
hardware, as well as automatic test vector and test program generation.

Kevin T. Kornegay

Robert W. Brodersen

Integrated Test Solutions for a System Design
Environment

This paper presents a technique for designing interacting finite state machines which will be totally self-checking
for any single stuck-at fault. In the proposed technique m-out-of-n codes are used for both primary output and
state assignments. In addition, the next state logic (NSL) for each submachine and the output logic (OL) are
realized such that any single stuck-at fault results in either single bit error or unidirectional multibit error at the
output. The proposed technique does not have any restriction on the way the NSL and the OL are implemented.

Fadi Busaba

Parag K. Lala

An Approach for Self-Checking Realization of
Interacting Finite State Machines

We present a design method (called STD architecture) to design large memories so that the test time does notincrease with the increasing size of memory. Large memories can be constructed by using several small blocksof memory. The memory address decoder is divided into two or more levels and designed such that during thetest mode all small memory blocks are accessed together. With the help of modified decoder, all small memoryblocks are tested in parallel using any standard test algorithm. In this design, time to test the whole memory isequal to the time required to test one small block. The proposed design is highly structured and hardware overheadis negligible. The basic idea is to exploit internal hardware for testing purpose. With the proposed method aconstant test time can be achieved irrespective of the memory size. STD architecture is applicable to memorychips as well as memory boards, and the design is suitable for fault detection as well as for fault diagnosis.

Rochit  Rajsuman

Kamal  Rajkanan

STD Architecture: A Practical Approach to TestM-Bits Random Access Memories

Built-in-self-test (BIST) response data can be compacted using a linear-feedback shift register (LFSR). Prior workhas indicated that the probability of aliasing tends to converge to 2-k for a polynomial of degree k and large testlength, and that primitive polynomials perform better than non-primitive polynomials. Nearly all analytical modelsand simulations have been based on the assumption that error occurrences are statistically-independent. Thispaper presents the first statistical results, based on fault simulation, that show that this convergence propertyholds for actual digital logic circuits and randomly-generated test vector sequences. However, it is shown thatthe average probability of aliasing is unsuitable as a design metric, and that a 95&#37; upper confidence limit (UCL)is more useful. This paper introduces a UCL for the loss of fault coverage due to test response compaction. Thetheoretical or &#8220;ideal&#8221; UCL is shown to match closely the empirically-derived UCL obtained by fault simulation.The result is that a tight lower bound on fault coverage for LFSR-based BIST configurations can be obtainedeasily. Fault coverage for a BIST configuration can be obtained without the LFSR, eliminating costly faultsimulation of the full structure with the LFSR. These results have been incorporated in the standard procedurefor fault coverage measurement.

Warren H. Debany

Mark J. Gorniak

Anthony R. Macera

Daniel E. Daskiewich

Kevin A. Kwiat

Heather B. Dussault

Empirical Bounds on Fault Coverage LossDue to LFSR Aliasing

Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the manyDFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paperwe explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flip-flopsand obtain reasonably high coverage. This approach has lower overhead in terms of test application timeand hardware area when compared to previous ones. Further enhancement of the controllability is obtained byusing multiple reset lines. The configuration of these multiple reset lines is described. This technique has beenevaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.

Ben  Mathew

Daniel G. Saab

Partial Reset: An Alternative DFT Approach

On-the-fly calculations of area and performance are a typical part of the computer-aided iterative design processin VLSI, which aims at a satisfactory tradeoff of various conflicting objectives, among which are test-generationtime and test-set size. However, determining test sets on-the-fly as one circuit is transformed into another isextremely difficult. Our goal is to add a test dimension to the design optimization process that complementsmethods concerned with area and performance optimization. We define a set of logic transformations that resultin easily computed changes to test sets. Test-set preserving (TSP) transformations preserve a combinational circuit’stest sets, while test-set altering (TSA) transformations introduce a minimum number of tests needed to maintaincompleteness. We illustrate our approach with a family of adders that share area-efficient tree structures anddiffer in the amount of carry-lookahead used to accelerate carry computation. Members include the ripple-carryadder, which has no lookahead, and the standard carry-lookahead adder, which exploits lookahead across allinputs. It is straightforward to derive area and performance measures for this class of adders. Given an n-bitadder with lookahead degree k, we determine a sequence of circuit transformations that produce the adder ofdegree k2 and test sets of minimum size. Optimal test sets of size k(logkn + 1) + 2 result for arbitrary n and k,which improve significantly upon previously reported tests.

Michael J. Batek

John P. Hayes

Optimal Testing and Design of Adders

Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and isnormally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Manyfaults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders ofmagnitude. Some of these faults may not manifest themselves as logical faults, and would not be detected bytraditional IC test techniques.In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due tonormal parameter variations. A statistical characterization of the problem is presented. This can be used todetermine the optimal size of partitions. A new information compression scheme is presented which can significantlyenhance resolution.

Yashwant K. Malaiya

Anura P. Jayasumana

Carol Q. Tong

Sankaran M. Menon

Resolution Enhancement in IDDQ Testingfor Large ICs

The logic behavior and performance of ECL gates under a set of defect models are examined. These are comparedwith equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaininga sufficiently high fault coverage, e.g., 79&#37; for ECL versus 54&#37; for BiCMOS and 69&#37; for CMOS equivalentgates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or NoiseMargin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay faulttesting yields the highest fault coverage for BiCMOS and CMOS gates (around 95&#37;). However, for equivalentECL gates to attain a fault coverage of around 98&#37;, both logical and NM fault testing have to be used.

M. O. Esonu

D.  Al-Khalili

C.  Rozon

Fault Characterization and Testability Analysis ofEmitter Coupled Logic and Comparison with CMOS&#38; BiCMOS Circuits

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VLSI Design