VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme

Table 1

Area and speed performance of one-level forward 2D DWT for 32×32 subimages.

Lifting scheme	Slices used	Speed (MHz)	Number of registers
Nonpipelined	836	54.45	611
Pipelined	1110	87.54	1670
Hybrid WP-P	836 [188]^*	75.75	611 [85]^*

^*denotes additional overhead for testing WP circuits.