(i) FPGA platform selection (D8) (ii) FPGA device selection (D7)
(i) FPGA platform selection (D8) (ii) FPGA device selection (D7)
Open issues
(i) Lack of FPGA platforms, where hardware designers must buy FPGA platform (D8) (ii) Hardware designers must develop and integrate their own IPs locally (D1, D2)
(i) Application designers should define a fixed limited time when they use the platform (ii) Feasibility of using a set of FPGA on a sharing time with a low number of application designers (iii) Hardware designers must develop and integrate their own IPs locally (D1, D2) (iv) Hardware designers should setup FPGA tools locally to simulate and implement their designs (D3, D4, D5) (v) The hardware designer must achieve the timing closure (D6)
(i) Hardware designers must develop and integrate their own IPs locally (D1, D2) (ii) Hardware designers should setup FPGA tools locally to simulate and implement their designs (D3, D4, D5) (iii) The hardware designer must achieve the timing closure (D6)
1Solved challenges with that the challenge is partially solved.