A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

<table class="table-group" id="tab2"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td class="align_left">Minimum</td><td class="align_center">Mode</td><td class="align_center">Average (SD)</td><td class="align_center">Maximum</td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td class="align_left">61,824</td><td class="align_center">61,824</td><td class="align_center">61,833.7 (13.7)</td><td class="align_center">61,854</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

<div>Statistics of clock cycle count required for DPR in the EU-swapping experiment.</div>

International Journal of Reconfigurable Computing

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Table 2

Table 2: A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor 