ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

<table class="table-group" id="tab7"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr class="thead"><td class="align_left"> </td><td class="align_center">FF</td><td class="align_center">LUT</td><td class="align_center">BRAM_18K</td></tr><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td class="align_left">HLS_video_downscaler</td><td class="align_center">1362</td><td class="align_center">2022</td><td class="align_center">15</td></tr><tr><td class="align_left">VHDL_video_downscaler</td><td class="align_center">2052</td><td class="align_center">1753</td><td class="align_center">12</td></tr><tr><td class="align_left">HLS_convolution_filter</td><td class="align_center">4968</td><td class="align_center">5958</td><td class="align_center">9</td></tr><tr><td class="align_left">VHDL_convolution_filter</td><td class="align_center">5136</td><td class="align_center">3925</td><td class="align_center">9</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

<div>Comparing HLS and hand-written VHDL implementations for video downscaler (16:1) and convolution filter.</div>

International Journal of Reconfigurable Computing

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Table 7

Table 7: ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures 