Research Article
FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach
Table 9
Implementation of the Improved Reconfigurable FSMIM architecture on the Virtex-6 speed-3 device in an iterative manner.
| Iteration No. | FSM included | #LUTs occupied | Maximum | Maximum | #LUTs occupied by the FSM | in the specific | in the specific | Operating | Path | (#LUTs in the current iteration | iteration | iteration | Frequency (MHz) | Delay (ns) | - #LUTs in the previous iteration) |
| | | 40 | 831.693 | 3.898 | 40 | | | 97 | 803.44 | 4.288 | 57 | | | 114 | 793.583 | 5.252 | 17 | | | 142 | 785.326 | 4.219 | 28 | | | 157 | 776.863 | 4.534 | 15 | | | 187 | 760.88 | 4.117 | 30 | | | 198 | 757.237 | 3.854 | 11 | | | 217 | 743.431 | 4.204 | 19 | | | 240 | 713.929 | 4.401 | 23 | | | 249 | 704.892 | 4.649 | 9 | | | 274 | 690.83 | 4.977 | 25 | | | 293 | 676.928 | 5.151 | 19 |
|
|
#LUTs number of LUTs occupied in ISE |