FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach

Table 8

Comparative analysis of the total computation time required by IGHA [6] and Improved-IGHA.

Iteration No.	FSM included	Total elapsed time	Total elapsed time	Total elapsed time for Improved-IGHA
	in the specific	for IGHA [6]	for state encoding	(Hrs)
	iteration	(Hrs)	tech. (ms)
		0	296.529	0
		25.34	214.468	25.34
		18.57	156.062	18.57
		48.65	338.560	48.65
		13.17	182.808	13.17
		32.43	293.894	32.43
		0.182	148.784	0.182
		30.409	249.509	30.409
		16.21	387.923	16.21
		4.38	167.144	4.38
		48.544	312.809	48.544
		48.654	326.406	48.654