| | Parameter | Description |
| | SoC | 1 core connected by shared-bus, IO-bus, MC, high-speed transceivers | | Core | 3 GHz, in-order super-scalar | | Branch predictor | Two levels (history length = 14 bits, pattern history
Table = 16 KiB, 8-cycle miss-prediction penalty) | | L1 cache | Private I-cache 32 KiB, private D-cache 32 KiB, 2 ways, 3-cycle latency | | L2 cache | Private 2, 8, 32, 64, 256, 1024 KiB, 4 ways, 5-cycle latency | | L3 cache | Shared 4 MiB, 4 ways, 20-cycle latency | | Coherence protocol | MOESI | | Main memory | 1 GiB, 100-cycle latency | | I-L1-TLB, d-L1-TLB | 64 entries, direct access, 1-cycle latency | | L2-TLB | 512 entries, direct access, 1-cycle latency | | Write/read queues | 200 Bytes each, 1-cycle latency |
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