Research Article
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)
Table 3
Comparison of different total DSE time of the classical design workflow for FPGAs (Figure
2-left) and our proposed methodology (Figure
2-right).
| Application | HLS + Synthesis (hours) (Figure 2-left) | Our framework (seconds) (Figure 2-right) |
| 2-way cache | 3 : 50 | 5 | Blocked matrix multiplication (DF-Threads, matrix size = 864, block size = 8, integer) | 4 : 25 | 8 | Fibonacci (DF-Threads, N = 35) | 1 : 40 | 8 |
|
|