Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Table 1

Key features of discussed HLS tools.

Tool	Owner	License	Input	Output	Domain	Testbench	SW/HW	Simulation	Floating point	Fixed point
LegUp [27]	LegUp computing	Commercial	C, C++	Verilog	All	Yes	Yes	HW	Yes	No
Bambu [28]	Politecnico di Milano	Academic	C	VHDL, Verilog	All	Yes	Yes	SW, HW	Yes	No
GAUT [29]	U. Bretagne sud	Academic	C, C++	VHDL, SystemC	DSP	Yes	No	HW	No	Yes
DWARV [30]	TU delft	Academic	C	VHDL	All	Yes	Yes	HW	Yes	Yes
Stratus HLS [31]	Cadence	Commercial	C, C++, SystemC	C, C++, SystemC	All	Yes	Yes	SW, HW	Yes	Yes
Intel HLS compiler [32]	Intel	Commercial	C, C++,	Verilog	All	No	No	SW, HW	Yes	Yes
Vivado HLS [18]	Xilinx	Commercial	C, C++, OpenCL, SystemC	VHDL, Verilog, SystemC	All	Yes	No	SW, HW	Yes	Yes
SDSoC [33]	Xilinx	Commercial	C, C++	VHDL, Verilog	All	No	Yes	SW, HW	Yes	Yes
SDAccel [34]	Xilinx	Commercial	C, C++, OpenCL	VHDL, Verilog, SystemVerilog	All	Yes	Yes	SW, HW	Yes	Yes

For the nonobvious columns, Testbench means the capability of automatic testbench generation. SW/HW means the support for the software/hardware co-design environment. Floating Point and Fixed Point are the supported data types for the arithmetic operations.