Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Figure 9

Level 2 architecture description of the cache model in COTSon by using the MYDSE toolset. In this design, the CPU is directly connected to both an Instruction Cache (“ic”) and a Data Cache (“dc”). The “ic” and “dc” caches are then connected to another level of caching, the L2 cache (“l2”), which is connected to the main memory (“mem”) through the “bus.”