Research Article
Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer
Table 1
1D-QHT implementation results on Arria 10AX115N4F45E3SG FPGA.
| | Number of pixels | Number of qubits | Resource utilization (%) | SDRAM (bytes) | Emulation time (sec) | | ALMs | BRAMs | DSPs |
| | 16 × 16 | 8 | 11 | 8 | 1 | 4 K | 0.00018 | | 32 × 32 | 10 | 11 | 8 | 1 | 16 K | 0.00071 | | 64 × 64 | 12 | 11 | 8 | 1 | 64 K | 0.00285 | | 128 × 128 | 14 | 11 | 8 | 1 | 256 K | 0.01139 | | 256 × 256 | 16 | 11 | 8 | 1 | 1 M | 0.04557 | | 512 × 512 | 18 | 11 | 8 | 1 | 4 M | 0.18226 | | 1024 × 1024 | 20 | 11 | 8 | 1 | 16 M | 0.72905 |
|
|
Total chip resources: NALM = 427,200; NBRAM = 2,713; NDSP = 1,518. Total on-board SDRAM memory: 2 parallel banks of 32 GB each. |
