SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 9

Influence of number of gates.

Gate numbers	Time	Speedup compared with SW	Speedup improvement
5 XOR 5 AND	18677	8.20	—
10 XOR 10 AND	14888	10.29	1.25
15 XOR 15 AND	12252	12.50	1.22

64-bit multiplication problem; 300 MHz main clock and 200 MHz local clock.