SIFO: Secure Computational Infrastructure Using FPGA Overlays
Table 3
Wire information for problems.
Problem
Wire
A wire
B gate
C gate
Max D
Wire/layer
6 bit adder
42
12
12
0
1
2.5
10 bit HD
140
55
50
5
7
6.4
30 bit HD
420
163
147
11
22
15.6
50 bit HD
700
293
269
24
37
21.9
8 bit mult
495
296
247
49
64
8.7
16 bit mult
2015
1232
1007
225
256
16.7
32 bit mult
8127
5024
4063
961
1024
32.6
64 bit mult
32639
20288
16319
3969
4096
64.6
10 4 bit sorting
5717
2968
2136
832
40
20.6
4 bit m_mult
16175
9700
8350
1350
2000
647.0
10 10 4 bit m_mult
31472
18768
16051
2717
3809
1165.6
8 bit m_mult
64375
39400
32850
6550
8000
1129.4
8 bit m_mult
517500
317600
263400
54200
64000
9078.9
4 bit m_mult
1050800
635200
541600
93600
128000
28400.0
A: 1-to-1 wire; B: gate with a one 1-to-1 wire from the adjacent layer; C: gate with a one 1-to-1 wire not from the adjacent layer; D: maximum number of 1-to-1 wires in a layer.