SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 11

Speedup results.

Problem	Sw (ms)	Time (µs)	Speedup
6 bit adder	2.06	45	45.78
10 bit HD	2.53	80	31.63
30 bit HD	4.08	171	23.86
50 bit HD	6.46	259	24.94
8 bit mult	9.22	293	31.47
16 bit mult	14.54	949	15.32
32 bit mult	33.76	3308	10.21
64 bit mult	153.13	12252	12.50
10 4 bit sort	21.12	2339	9.03
4 bit m_mult	60.66	5830	10.40
4 bit m_mult	220.81	11286	19.56
8 bit m_mult	203.86	24128	8.45
8 bit m_mult	1060.63	170895	6.21
4 bit m_mult	2170.88	340698	6.37