Research Article
On a Real-Time Blind Signal Separation Noise Reduction System
Table 3
Implementation results of BSS.
| | FPGA device | XC4VSX55-12 | XC2VP30-7 |
| | Slices used | 5937 (12%) | 8916(32%) |
| | DSP48/MULT used | 72 (14%) | 72 (52%) |
| | Block RAM used | 8 (2%) | 8 (5%) |
| | Frequency (MHz) | 184.8 | 165.9 |
|
|
