Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

Table 3

DRAM energy consumption baseline vs tile-hopping.

EPR CW^∘ Read
(Baseline)	4.46	5.77	7.12
EPR CW Read
Tile-Hopping	2.54	2.95	3.36
(Proposed)
Reduction

Energy per read (EPR).
Column-wise memory access (CW).