Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/ijrc/volume-2018/1403181/figures/1403181.fig.0010a.svgz" name="1403181.fig.0010a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>2D FFT performance: DRAM tile-hopping</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/ijrc/volume-2018/1403181/figures/1403181.fig.0010b.svgz" name="1403181.fig.0010b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>2D FFT with EAR performance: PSD versus OPSD</td></tr></table>

<div>Performance evaluation in terms of frames per second for (a) 2D FFTs with tile-hopping memory pattern. (b) 2D FFTs with edge artifact removal (EAR) using OPSD. The performance evaluation shows the significance of the two optimizations proposed. Both axes are on a log scale.</div>

International Journal of Reconfigurable Computing

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Figure 10

Figure 10: Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal 