Research Article
Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders
Table 4
Synthesis results and comparison with related works.
| Works | Technology | Hardware resources | Number of cycles | Max. frequency | Number of HD1080p frames/s | Frequency to process HD1080p@30 fps |
| Wang et al. [4] | UMC 0.18 μm | 10,302 gates | 416 | 66 MHz | 31 | 62.21 MHz | Kao et al. [5] | TSMC 0.13 μm | 11,229 gates | 672 | 75 MHz | Not supported | Not supported | Lin et al. [6] | TSMC 0.13 μm |
*94,700 gates | 560 | 140 MHz | 30 | 140 MHz |
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This work
| FPGA | 3,267 ALUTs 2,312 DLRs | 36 | 98.43 MHz | 335 | 8.26 MHz | TSMC 0.18 μm | 28,518 gates | 36 | 129.1 MHz | 439 | 8.26 MHz |
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*Hardware resources considering the complete intra-coder.
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