An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing

<table>Example data flow of an AIREN hardware base <span style="font-family:monospace">MPI_Send</span>/<span style="font-family:monospace">MPI_Recv</span>.</table>

International Journal of Reconfigurable Computing

fig8

Figure 8

Figure 8: An Evaluation of an Integrated On-Chip/Off-Chip Network for
High-Performance Reconfigurable Computing 

International Journal of Reconfigurable Computing

An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

Figure 8