Research Article
Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems
Table 1
Synthesis results of the ST/DDST transmitter.
| FPGA resource | Used | Available | Utilization |
| Frequency | 160.12 | MHz | ā | Slice registers | 141 | 69120 | <1% | Slice LUTs | 437 | 69120 | <1% | Fully used LUT-FF pairs | 134 | 444 | 30% | IOBs | 46 | 640 | 7% | BRAMs | 4 | 148 | 2% |
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