Research Article
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
Algorithm 1
Pseudocode in
random logic mapping.
program VGLC_HeteroMap(network) | for each PI to PO
do is node */ | min_label := ; | if n equal macro then | calculate Label(n) and Cut(n) as macro block; | else | for of input for CF and Misc. Logic do | calculate Label(n) and Cut(n) as delay and of inputs; | if misc. function then | if pattern is mismatch then continue; | if Label(n) min_label then | min_label := Label(n); min_cut := Cut(n); | end if | end for | Label(n) := min_label; Cut(n) := min_cut; | end for | mapping using selected function; | end program |
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