Jean-Baptiste Begueret

Thierry Taris

International Conference on Electronics, Circuits, and Systems

We propose a time-consistent video segmentation algorithm designed for real-time implementation.
Our algorithm is based on a region merging process that combines both spatial and motion information. 
The spatial segmentation takes benefit of an adaptive decision rule and a specific order of merging. 
Our method has proven to be efficient for the segmentation of natural images with few parameters to be set.
Temporal consistency of the segmentation is ensured by incorporating motion information through the use of an improved change-detection mask. This mask is designed using both illumination differences between frames and region segmentation of the previous frame. By considering both pixel and region levels, we obtain a particularly efficient algorithm at a low computational cost, allowing its implementation in real-time on the TriMedia processor for CIF image sequences.

M. El Hassani

S. Jehan-Besson

L. Brun

M. Revenu

M. Duranton

D. Tschumperl&#233;

D. Rivasseau

A Time-Consistent Video Segmentation Algorithm Designed for Real-Time Implementation

This study presents a novel design approach combining wave 
pipelining and self reset logic, which provides an elegant 
solution at high-speed data throughput with significant savings in 
power and area as compared with other dynamic CMOS logic 
implementations. To overcome some limitations in SRL art, we 
employ a new SRL family, namely, dual-rail self reset logic with 
input disable (DRSRL-ID).  These gates depict fairly constant 
timing parameters, specially the width of the output pulse, for 
varying fan-out and logic depth, helping accommodate process, 
supply voltage,  and temperature variations (PVT). These 
properties simplify the implementation of wave pipelined circuits. 
General timing analysis is provided and compared with previous 
implementations. Results of circuit implementation are presented 
together with conclusions and future work.

Miguel E. Litvin

Samiha Mourad

Wave Pipelining Using Self Reset Logic

The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. 
    A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. 
    The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account.
    The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25&#x2009;<svg style="vertical-align:-2.29482pt;width:9.6374998px;" id="M1" height="9.6750002" version="1.1" viewBox="0 0 9.6374998 9.6750002" width="9.6374998"  xmlns="http://www.w3.org/2000/svg">
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</svg>m CMOS technology at 3.3&#x2009;V. The critical delay for the proposed adder is 3.4&#x2009;nanoseconds. The simulation results show that the proposed adder is 18<svg style="vertical-align:-0.23827pt;width:11.8px;" id="M2" height="11.45" version="1.1" viewBox="0 0 11.8 11.45" width="11.8"  xmlns="http://www.w3.org/2000/svg">
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</svg> faster than the current fastest carry-skip adder.

Yu Shen Lin

Damu Radhakrishnan

Delay Efficient 32-Bit Carry-Skip Adder

The content-based access of CAMs makes them of great interest in lookup-based operations. However, the large amounts of parallel comparisons required cause an expensive cost in power dissipation. In this work, we present a novel banked precomputation-based architecture for low-power and storage-demanding applications where the reduction of both dynamic and leakage power consumption is addressed. Experimental results show that the proposed banked architecture reduces up to an 89% of dynamic power consumption during the search process while the leakage power consumption is also minimized up to a 91%.

Pedro Echeverr&#xed;a

Jos&#xe9; L. Ayala

Marisa L&#xf3;pez-Vallejo

Power Considerations in Banked CAMs: A Leakage Reduction Approach

This paper presents the design and implementation of a 2K/4K/8K multiple mode FFT core for DVB-T/DVB-H receivers. The proposed core is based on a pipeline radix-2<sup>2</sup> SDF architecture. The necessary changes in the radix-2<sup>2</sup> SDF architecture to achieve an efficient FFT implementation are detailed. Quantization effects and timing design parameters are analyzed for DVB-T/DVB-H. Area and power results are provided for the proposed core.

A. Cort&#xe9;s

I. V&#xe9;lez

I. Zalbide

A. Irizar

J. F. Sevillano

An FFT Core for DVB-T/DVB-H Receivers

Multi-input multi-output (MIMO) systems combined
with orthogonal frequency-division multiplexing (OFDM)
gained a wide popularity in wireless applications due to the
potential of providing increased channel capacity and robustness
against multipath fading channels. However these advantages
come at the cost of a very high processing complexity and
the efficient implementation of MIMO-OFDM receivers is today
a major research topic. In this paper, efficient architectures
are proposed for the hardware implementation of the main
building blocks of a MIMO-OFDM receiver. A sphere decoder
architecture flexible to different modulation without any loss in
BER performance is presented while the proposed matrix factorization
implementation allows to achieve the highest throughput
specified in the IEEE 802.11n standard. Finally a novel <svg style="vertical-align:-3.25793pt;width:17.375px;" id="M1" height="14.3875" version="1.1" viewBox="0 0 17.375 14.3875" width="17.375"  xmlns="http://www.w3.org/2000/svg">
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</svg> sphere
decoder approach is presented, which allows for the realization of
new golden space time trellis coded modulation (GST-TCM)
scheme. Implementation cost and offered throughput are provided
for the proposed architectures synthesized on a 0.13&#x2009;<svg style="vertical-align:-2.29482pt;width:20.737499px;" id="M2" height="9.875" version="1.1" viewBox="0 0 20.737499 9.875" width="20.737499"  xmlns="http://www.w3.org/2000/svg">
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</svg> CMOS
standard cell technology or on advanced FPGA devices.

Barbara Cerato

Guido Masera

Emanuele Viterbo

Enabling VLSI Processing Blocks for  MIMO-OFDM Communications

We present an IP-core called PHCA which stands for programmable hardware cellular automaton. PHCA is a hardware implementation of a general purpose cellular automaton (CA) entirely programmable. The heart of this structure is a PE array with reconfigurable side links allowing the implementation of a 2D CA or a 1D CA. As an illustration of a PHCA program, we present the implementation of a symmetric cryptography algorithm called ISEA for Ising spin encryption algorithm. Indeed ISEA is based on a 2D Ising spin lattice presenting random series of disordered spin configurations. The main idea of ISEA is to use this disorder to encrypt data. Efficiency of ISEA and PHCA implementation results are given.

Samuel Charbouillot

Annie P&#xE9;rez

Daniele Fronte

A Programmable Hardware Cellular Automaton:  Example of Data Flow Transformation

This paper presents an FPGA implementation of a high-performance rank filter for video and image processing. The architecture exploits the features of current FPGAs and offers tradeoffs between complexity and performance. By maximizing the operating frequency, the complexity of the filter structure can be considerably reduced compared to previous 2D architectures.

P&#233;ter  Sz&#225;nt&#243;

G&#225;bor  Szed&#337;

B&#233;la  Feh&#233;r

High-Performance Timing-Driven Rank Filter

Future 4th Generation (4G) wireless multiuser communication systems will have to provide advanced multimedia services to an increasing number of users, making good use of the scarce spectrum resources. Thus, 4G system design should  pursue both higher-transmission bit rates and higher spectral efficiencies. To achieve this goal, multiple antenna systems are called to play a crucial role.  In this contribution we address the implementation in FPGAs of a multiple-input multiple-output (MIMO) decoder embedded in a prototype of a 4G mobile receiver.  This MIMO decoder is part of a multicarrier code-division multiple-access (MC-CDMA) radio system, equipped with multiple antennas at both ends of the link, that is able to handle up to 32 users and provides raw transmission bit-rates up to 125 Mbps. The task of the MIMO decoder is to appropriately combine the signals simultaneously received on all antennas to construct an improved signal, free of interference, from which to estimate the transmitted symbols. A comprehensive explanation of the complete design process is provided, including architectural decisions, floating-point to fixed-point translation, and description of the validation procedure. We also report implementation results using FPGA devices of the Xilinx Virtex-4 family.

Alberto Jiménez-Pacheco

Ángel Fernández-Herrero

Javier Casajús-Quirós

Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver

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