Research Article

Characterizing the Effects of Intermittent Faults on a Processor for Dependability Enhancement Strategy

Table 10

SDC ((a) for NET and (b) for REG).
(a) SDC for NET (%)

Functional BlocksUnitLDST testbenchEXU testbench
SDCSDC′SDC′′SDCSDC′SDC′′

ControlPKU15.60.70.614.10.10.1
AGEN9.20.20.18.80.10.1
Decoder5.80.80.75.91.21.2
ExecutionALU4.11.11.01.50.20.0
StorageIRF3.20.80.72.60.10.1
Average7.60.70.66.60.30.3

(b) SDC for REG (%)

Functional BlocksUnitLDST testbenchEXU testbench
SDCSDC′SDC′′SDCSDC′SDC′′

ControlPKU4.10.90.95.30.10.1
AGEN0.20.10.00.70.00.0
Decoder2.10.10.00.10.10.0
ExecutionALU0.10.00.00.00.00.0
StorageIRF0.10.10.00.00.00.0
Average1.30.20.21.20.00.0