TY - JOUR A2 - Yu, F. A2 - Shu, J. AU - Wang, Chao(Saul) AU - Fu, Zhong-Chuan AU - Chen, Hong-Song AU - Wang, Dong-Sheng PY - 2014 DA - 2014/04/28 TI - Characterizing the Effects of Intermittent Faults on a Processor for Dependability Enhancement Strategy SP - 286084 VL - 2014 AB - As semiconductor technology scales into the nanometer regime, intermittent faults have become an increasing threat. This paper focuses on the effects of intermittent faults on NET versus REG on one hand and the implications for dependability strategy on the other. First, the vulnerability characteristics of representative units in OpenSPARC T2 are revealed, and in particular, the highly sensitive modules are identified. Second, an arch-level dependability enhancement strategy is proposed, showing that events such as core/strand running status and core-memory interface events can be candidates of detectable symptoms. A simple watchdog can be deployed to detect application running status (IEXE event). Then SDC (silent data corruption) rate is evaluated demonstrating its potential. Third and last, the effects of traditional protection schemes in the target CMT to intermittent faults are quantitatively studied on behalf of the contribution of each trap type, demonstrating the necessity of taking this factor into account for the strategy. SN - 2356-6140 UR - https://doi.org/10.1155/2014/286084 DO - 10.1155/2014/286084 JF - The Scientific World Journal PB - Hindawi Publishing Corporation KW - ER -