A Chaotic Multi-Objective Runge–Kutta Optimization Algorithm for Optimized Circuit Design

Figure 8

(a) CMRUN, (b) CMRUN Pareto fitness plot, (c) NSGA-II, (d) MOPSO, (e) MOBA, (f) SPEA-2, (g) MOMA, (h) NSMFO, (i) MOEAD, (j) MOFA, (k) MOCS, (l) MOFPA, and (m) NSGA-II/MOPSO.

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