480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications

Figure 5

Block diagram of DLL1 and DLL2. In DLL1, 𝐹_IN and 𝐹_O are 12 MHz and 60 MHz, respectively. The VCDL generates 10-tap 12 MHz output signals. The capacitor is 10 pF. In DLL2, 𝐹_IN and 𝐹_O are 60 MHz and 480 MHz, respectively. The VCDL generates 16-tap 60 MHz output signals. The capacitor is 0.5 pF.