Research Article

480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications

Figure 22

Postlayout simulation results from VCDL and EC applied to DLL1 for variable 𝑉 C . The simulation condition is ff/1.30 V/−40°C.
267247.fig.0022a
(a) OUT10
267247.fig.0022b
(b) F O 1