Design Considerations for Autocalibrations of Wide-Band <svg style="vertical-align:-0.0pt;width:27.9px;" id="M1" height="15.025" version="1.1" viewBox="0 0 27.9 15.025" width="27.9" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.022,-0,0,-.022,.062,14.975)"><path id="x394" d="M600 0h-557v24l268 633l28 8l261 -641v-24zM497 50l-194 489l-196 -489h390z" /></g><g transform="matrix(.022,-0,0,-.022,14.431,14.975)"><path id="x3A3" d="M570 168l-39 -168h-498v23l262 301l-248 304v22h471q4 -71 11 -146l-29 -4q-17 65 -37 88q-12 15 -36 20.5t-79 5.5h-181l211 -256l-243 -287h280q51 0 77 20.5t49 83.5z" /></g></svg> Fractional-<svg style="vertical-align:-0.144pt;width:19.7125px;" id="M2" height="14.875" version="1.1" viewBox="0 0 19.7125 14.875" width="19.7125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.022,-0,0,-.022,.062,14.638)"><path id="x1D441" d="M857 650l-6 -28q-44 -4 -61.5 -16.5t-29.5 -48.5q-11 -32 -37 -166l-78 -399h-29l-351 537h-4l-56 -276q-24 -120 -24 -164q0 -35 17.5 -46t75.5 -15l-6 -28h-245l7 28q41 2 62 14t31 44q10 30 41 171l53 245q8 44 6.5 60.5t-14.5 33.5q-10 15 -27 19.5t-64 6.5l6 28h153
l350 -516h5l48 257q25 131 25 171q0 34 -17.5 45t-77.5 15l7 28h240z" /></g></svg> PLL Synthesizers

<table>Behavioral simulation results for the proposed autocalibration. (a) <svg height="15.4" id="M167" style="vertical-align:-3.39069pt" version="1.1" viewbox="0 0 34.712502 15.4" width="34.712502" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
<g transform="matrix(.017,-0,0,-.017,.062,11.112)"><path d="M730 650l-8 -28q-52 -4 -72 -18t-64 -77q-79 -113 -321 -539h-33l-119 541q-13 59 -29.5 73t-66.5 20l7 28h245l-8 -28l-28 -5q-33 -6 -40.5 -15.5t-0.5 -38.5l102 -450h2q191 320 246 430q21 42 15.5 56t-43.5 19l-31 4l7 28h240z" id="x1D449"></path></g>
<g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><path d="M298 36l-68 -35q-25 -13 -42 -13q-98 0 -98 119v290h-69l-4 11l28 29h45v72l65 67l14 -2v-137h113q8 -8 6 -21t-12 -19h-107v-256q0 -96 59 -96q29 0 61 17z" id="x74"></path></g><g transform="matrix(.012,-0,0,-.012,16.197,15.187)"><path d="M518 50v-26q-32 -4 -77 -16l-37 -11t-33 -9l-6 6v71q-56 -42 -74 -52q-43 -25 -77 -25q-55 0 -89.5 36.5t-34.5 112.5v196q0 38 -6.5 48.5t-26.5 15.5l-28 6v23q19 1 72 7q59 9 71 11q-3 -31 -3 -145v-135q0 -113 88 -113q59 0 108 48v234q0 38 -8 49t-34 15l-36 6v23
q44 2 90 8q37 4 67 10v-334q0 -37 8.5 -47t38.5 -12z" id="x75"></path></g><g transform="matrix(.012,-0,0,-.012,22.515,15.187)"><path d="M524 0h-209v26q44 5 55 18t11 65v167q0 114 -91 114q-50 0 -109 -51v-235q0 -50 10 -61.5t55 -16.5v-26h-217v26q51 5 62 17t11 61v206q0 47 -9.5 58.5t-50.5 19.5v23q82 15 139 40v-79l67 47q47 30 83 30q60 0 94.5 -40t34.5 -112v-193q0 -50 10 -61.5t54 -16.5v-26z
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</svg> and VCO cap bank code during autocalibration. (b) <svg height="15.4" id="M168" style="vertical-align:-3.39069pt" version="1.1" viewbox="0 0 34.712502 15.4" width="34.712502" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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<g transform="matrix(.012,-0,0,-.012,12.675,15.187)"><path d="M298 36l-68 -35q-25 -13 -42 -13q-98 0 -98 119v290h-69l-4 11l28 29h45v72l65 67l14 -2v-137h113q8 -8 6 -21t-12 -19h-107v-256q0 -96 59 -96q29 0 61 17z" id="x74"></path></g><g transform="matrix(.012,-0,0,-.012,16.197,15.187)"><path d="M518 50v-26q-32 -4 -77 -16l-37 -11t-33 -9l-6 6v71q-56 -42 -74 -52q-43 -25 -77 -25q-55 0 -89.5 36.5t-34.5 112.5v196q0 38 -6.5 48.5t-26.5 15.5l-28 6v23q19 1 72 7q59 9 71 11q-3 -31 -3 -145v-135q0 -113 88 -113q59 0 108 48v234q0 38 -8 49t-34 15l-36 6v23
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" id="x6E"></path></g><g transform="matrix(.012,-0,0,-.012,28.976,15.187)"><path d="M380 106l15 -22q-42 -52 -87 -74t-76 -22q-89 0 -142 62t-53 151q0 103 66 175q67 73 146 73h1q61 0 105.5 -46.5t44.5 -105.5q0 -16 -4.5 -22.5t-18.5 -9.5q-54 -10 -262 -17q1 -95 46 -143.5t104 -48.5q61 0 115 50zM225 412q-35 0 -64.5 -32.5t-40.5 -90.5q83 0 170 3
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</svg> for the total locking process for 3900 MHz target frequency.</table>

Journal of Electrical and Computer Engineering

fig14

Figure 14

Figure 14: Design Considerations for Autocalibrations of Wide-Band <svg style="vertical-align:-0.0pt;width:27.9px;" id="M1" height="15.025" version="1.1" viewBox="0 0 27.9 15.025" width="27.9" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.022,-0,0,-.022,.062,14.975)"><path id="x394" d="M600 0h-557v24l268 633l28 8l261 -641v-24zM497 50l-194 489l-196 -489h390z" /></g><g transform="matrix(.022,-0,0,-.022,14.431,14.975)"><path id="x3A3" d="M570 168l-39 -168h-498v23l262 301l-248 304v22h471q4 -71 11 -146l-29 -4q-17 65 -37 88q-12 15 -36 20.5t-79 5.5h-181l211 -256l-243 -287h280q51 0 77 20.5t49 83.5z" /></g></svg> Fractional-<svg style="vertical-align:-0.144pt;width:19.7125px;" id="M2" height="14.875" version="1.1" viewBox="0 0 19.7125 14.875" width="19.7125" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.022,-0,0,-.022,.062,14.638)"><path id="x1D441" d="M857 650l-6 -28q-44 -4 -61.5 -16.5t-29.5 -48.5q-11 -32 -37 -166l-78 -399h-29l-351 537h-4l-56 -276q-24 -120 -24 -164q0 -35 17.5 -46t75.5 -15l-6 -28h-245l7 28q41 2 62 14t31 44q10 30 41 171l53 245q8 44 6.5 60.5t-14.5 33.5q-10 15 -27 19.5t-64 6.5l6 28h153
l350 -516h5l48 257q25 131 25 171q0 34 -17.5 45t-77.5 15l7 28h240z" /></g></svg> PLL Synthesizers 

Journal of Electrical and Computer Engineering

Design Considerations for Autocalibrations of Wide-Band Fractional- PLL Synthesizers

Figure 14