Efficient Algorithms for Optimal 4-Bit Reversible Logic System Synthesis

Table 1

True table.

Input				Output
⟨𝑥2,𝑥1,𝑥0⟩2	𝑥2	𝑥1	𝑥0	⟨𝑦2,𝑦1,𝑦0⟩2	𝑦2	𝑦1	𝑦0
0	0	0	0	2	0	1	0
1	0	0	1	6	1	1	0
2	0	1	0	0	0	0	0
3	0	1	1	1	0	0	1
4	1	0	0	7	1	1	1
5	1	0	1	3	0	1	1
6	1	1	0	5	1	0	1
7	1	1	1	4	1	0	0