Comprehensive Review and Comparative Analysis of Hardware Architectures for Sobel Edge Detector

Table 1

FPGA resource utilization comparison.

Architecture	Logic; Slices	LUTs	Registers	LUT FF; Pairs	Route-thrus
I	24	83	23	83	2
II	31	96	77	97	0
III	42	128	1	128	8
IV	53	137	141	172	1