Research Article

A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm

Table 4

Execution time of our architecture and software versions.

Query length BLASTp TBLASTn BLASTx TBLASTx
ST(ms) HT(ms) ST(ms) HT(ms) ST(ms) HT(ms) ST(ms) HT(ms)

128 1901 1050 3203 153 1594 1030 4031 163
256 3087 1058 3641 167 2641 1042 5906 198
512 5603 1092 5156 202 4378 1074 9978 270
1 K 9327 1150 9891 254 7828 1135 16266 351
2 K 17814 1220 15438 360 13187 1210 27703 462
3 K 25132 1490 20328 436 18875 1331 37500 536