Selected Papers from the Southern Programmable Logic Conference (SPL2010)
Selected Papers from the Southern Programmable Logic Conference (SPL2010)
Description
SPL is the austral meeting point for researchers interested on FPGA technology. The 6th SPL continues the successful tradition of the previous editions and will be hosted by the Electronics and Systems Department, Federal University of Pernambuco, in the city of Ipojuca, Porto de Galinhas beach, State of Pernambuco, Brazil, from March 24th to 26th, 2010.
SPL 2010 organization has the IEEE Circuits and Systems Society (CAS) technical co-sponsorship. The SPL web site is: http://www.splconf.org/
The purpose of this special issue is to provide an opportunity for researchers, engineers, and designers to report recent advances in this important area of reconfigurable logic and applications using FPGAs.
Topics of interest for this special issue include, but are not limited to, the following:
- Design Methodology (Low-Power Design, High-speed Techniques, Physical Design, Synchronization and Self-timed Systems, Dynamic and run-time reconfiguration, Reconfigurable embedded systems, Field-programmable analogue arrays, Interconnects and NoCs)
- FPGA in Education (Roadmap of programmable logic, Teaching reconfigurable systems, History and surveys of programmable logic, Emerging device technologies, Tutorials)
- Platform-based Design (Embedded Processors, Custom Computers, IP Cores, Java, Handel-C, System-C)
- Applications (Robotics, Artificial vision, Communications/networking, Cryptography, Bioinformatics, Application acceleration, Evolvable and bio-inspired applications, Rapid prototyping )
- Custom Computers and DSPs (Computer Arithmetic, Digital Signal Processing, Software Radio, FCCMs)
- EDA Tools (Logic and Architectural, Synthesis, Modeling and Simulation, Emulation, Formal Methods in System Design, CAD for reconfigurable architectures, System-level design methods, Testing, verification and benchmarking, Hardware/software codesign)
- Aerospace Applications (Design verification and validation, Reliability and fault tolerance, FIT rates analysis, Qualification process, Device obsolescence, High-reliability processor cores, Noise, radiation effects and EMC, Experiences and lessons learned)
Submission to this special issue is limited to the participants of the SPL 2010 conference who have been invited to submit to this issue.
The criteria for invitations include: (1) the evaluation of SPL2010 program committee (only very good rated papers in SPL evaluation system), (2) the relevance of the topics, (3) a positive impression and comments in the presentation during the conference. The invitation to submit an extended version to the Special Issue does not guarantee that the paper will be published. In particular, submissions will be reviewed by at least 3 external referees to ensure that they meet the standard required to be published in the journal.
Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/ijrc/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable: