Gustavo Sutter

Richard Katz

Selected Papers from SPL 2008: Programmable Logic and Applications

The robustness of the human visual system recovering motion estimation in almost any visual situation is enviable, performing enormous calculation tasks continuously, robustly, efficiently, and effortlessly. There is obviously a great deal we can learn from our own visual system. Currently, there are several optical flow algorithms, although none of them deals efficiently with noise, illumination changes, second-order motion, occlusions, and so on. The main contribution of this work is the efficient implementation of a biologically inspired motion algorithm that borrows nature templates as inspiration in the design of architectures and makes use of a specific model of human visual motion perception: Multichannel Gradient Model (McGM). This novel customizable architecture of a neuromorphic robust optical flow can be constructed with FPGA or ASIC device using properties of the cortical motion pathway, constituting a useful framework for building future complex bioinspired systems running in real time with high computational complexity. This work includes the resource usage and performance data, and the comparison with actual systems. This hardware has many application fields like object recognition, navigation, or tracking in difficult environments due to its bioinspired and robustness properties.

Guillermo Botella

Manuel Rodríguez

Antonio García

Eduardo Ros

Neuromorphic Configurable Architecture for Robust Motion Estimation

This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.

Chi Wai Yu

Julien Lamoureux

Steven J. E. Wilton

Philip H. W. Leong

Wayne Luk

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

Duarte L. Oliveira

Marius Strum

Sandro S. Sato

Burst-Mode Asynchronous Controllers on FPGA

This paper presents the design and implementation of an automatically generated mathematical unit, from a program developed in Java that describes the VHDL circuit, ready to be synthesized with the Xilinx ISE tool. The core contains diverse complex operations such as mathematical functions including sine and cosine, among others. The proposed unit is used to synthesize a sliding mode controller for a magnetic levitation system. This kind of systems is used in industrial applications requiring high level of mathematical calculations in small time periods. The core is designed to calculate trigonometric and arithmetic operations in such a way that each function is performed in a clock cycle. In this paper, the results of the mathematical core are shown in terms of implementation, utilization, and application to control a magnetic levitation system.

Juan Jos&#233; Raygoza-Panduro

Susana Ortega-Cisneros

Jorge Rivera

Alberto de la Mora

Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System

This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when
targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus
allowing a designer to concentrate more on an algorithm description and less on hardware-specific implementation
details. The first algorithm is a source-level transformation implementing function exlining&#x02014;where a separate block of hardware implements a function and is shared between multiple calls to the
function. The second is a novel algorithm for mapping arrays to memories which involves assigning array
accesses to memory ports such that no port is ever accessed more than once in a clock cycle. This algorithm
assigns accesses to read/write only ports and read-write ports concurrently, solving the assignment problem
more efficiently for a wider range of memories compared to existing methods. Both optimisations operate
on a high-level program representation and have been implemented in a commercial SystemC compiler.
Experiments show that in suitable circumstances these techniques result in significant reductions in logic
utilisation for FPGAs.

Johan Ditmar

Steve McKeever

Alex Wilson

Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation

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International Journal of Reconfigurable Computing

Selected Papers from SPL 2008 - Programmable Logic and Applications

Selected Papers from SPL 2008 - Programmable Logic and Applications

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