Lionel Torres

Cesar Torres

Selected Papers from ReConFig 2008

This paper presents the OveRSoC project. The
objective is to develop an exploration and validation methodology
of embedded Real Time Operating Systems (RTOSs) for Reconfigurable
System-on-Chip-based platforms. Here, we describe the
overall methodology and the corresponding design environment.
The method is based on abstract and modular SystemC models
that allow to explore, simulate, and validate the distribution of
OS services on this kind of platform. The experimental results
show that our components accurately model the dynamic and
deterministic behavior of both application and RTOS.

Beno&#xee;t Miramond

Emmanuel Huck

Fran&#xe7;ois Verdier

Amine Benkhelifa

Bertrand Granado

Thomas Lefebvre

Mehdi A&#xef;chouch

Jean Christophe Prevotet

Yaset Oliva

Daniel Chillet

S&#xe9;bastien Pillement

OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms

We consider here the feasibility of gathering multiple computational resources by means of decentralized and simple local rules. We study such decentralized gathering by means of a stochastic model inspired from biology: the aggregation of the Dictyostelium discoideum cellular slime mold. The environment transmits information according to a reaction-diffusion mechanism and the agents move by following excitation fronts. Despite its simplicity this model exhibits interesting properties of self-organization and robustness to obstacles. We first describe the FPGA implementation of the environment alone, to perform large scale
and rapid simulations of the complex dynamics of this reaction-diffusion model. Then we describe the FPGA implementation of the environment together with the agents, to study the major challenges that must be solved when designing a fast embedded implementation of the decentralized gathering model. We analyze the results according to the different goals of these hardware implementations.

Bernard Girau

C&#xe9;sar Torres-Huitzil

Nikolaos Vlassopoulos

Jos&#xe9; Hugo Barr&#xf3;n-Zambrano

Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs

Biological sequence alignment is an essential tool used in molecular biology and biomedical applications. The growing volume of genetic data and the complexity of sequence alignment present a challenge in obtaining alignment results
in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

Scott Lloyd

Quinn O. Snell

Hardware Accelerated Sequence Alignment with Traceback

3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

Jose Hugo Barron-Zambrano

Fernando Martin del Campo-Ramirez

Miguel Arias-Estrada

Parallel Processor for 3D Recovery from Optical Flow

This work proposes an exact ILP formulation for the task scheduling problem on a 2D dynamically and partially reconfigurable architecture. Our approach takes physical constraints of the target device that is relevant for reconfiguration into account. Specifically, we consider the limited number of reconfigurators, which are used to reconfigure the device. This work also proposes a reconfiguration-aware heuristic scheduler, which exploits configuration prefetching, module reuse, and antifragmentation techniques. We experimented with a system employing two reconfigurators. This work also extends the ILP formulation for a HW/SW Codesign scenario. A heuristic scheduler for this extension has been developed too. These systems can be easily implemented using standard FPGAs. Our approach is able to improve the schedule quality by 8.76&#37; on average (22.22&#37; in the best case). Furthermore, our heuristic scheduler obtains
the optimal schedule length in 60&#37; of the considered cases. Our extended analysis demonstrated that HW/SW codesign can indeed lead to significantly better results. Our experiments show that by using our proposed HW/SW codesign method, the schedule length of applications can be reduced by a factor of 2 in the best case.

F. Redaelli

M. D. Santambrogio

S. Ogrenci Memik

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures

We address the 
                  automatic synthesis of DSP algorithms using 
                  FPGAs. Optimized fixed-point 
implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath
formed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resource
usage metric that enables an efficient distribution of logic fabric and embedded DSP resources.
The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point
datapaths and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed-point datapath
leads to improvements up to 35%. And, the wise mapping of operations to FPGA resources (logic fabric and embedded
blocks), thanks to the proposed resource usage metric, leads to improvements up to 54%.

Gabriel Caffarena

Juan A. López

Gerardo Leyva

Carlos Carreras

Octavio Nieto-Taladriz

Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs

An automated design approach for multiprocessor systems
on FPGAs is presented which customizes architectures
for parallel programs by simultaneously solving
the problems of task mapping, resource allocation, and
scheduling. The latter considers effects of fixed-priority
preemptive scheduling in order to guarantee real-time
requirements, hence covering a broad spectrum of embedded
applications. Being inherently a combinatorial
optimization problem, the design space is modeled using
linear equations that capture high-level design parameters.
A comparison of two methods for solving resulting problem
instances is then given. The intent is to study how well
recent advances in propositional satisfiability (SAT) and
thus Answer Set Programming (ASP) can be exploited to
automate the design of flexible multiprocessor systems.
Integer Linear Programming (ILP) is taken as a baseline,
where architectures for IEEE 802.11g and WCDMA
baseband signal processing are synthesized. ASP-based
synthesis used a few seconds in the solver, faster by three
orders of magnitude compared to ILP-based synthesis,
thereby showing a great potential for solving difficult
instances of the automated synthesis problem.

Harold Ishebabi

Philipp Mahr

Christophe Bobda

Martin Gebser

Torsten Schaub

Answer Set versus Integer Linear Programming for  Automatic Synthesis of Multiprocessor Systems from  Real-Time Parallel Programs

Modern High-End Computing systems frequently include FPGAs as compute accelerators. These programmable logic devices now support disk controller IP cores which offer the ability to introduce new, innovative functionalities that, previously, were not practical. This article describes one such innovation: a filesystem implemented in hardware. This has the potential of improving the performance of data-intensive applications by connecting secondary storage directly to FPGA compute accelerators. To test the feasibility of this idea, a Hardware Filesystem was designed with four basic operations (open, read, write, and delete). Furthermore, multi-disk and RAID-0 (striping) support has been implemented as an option in the filesystem. A RAM Disk core was created to emulate a SATA disk
drive so results on running FPGA systems could be readily measured. By varying the block size from 64 to 4096 bytes, it was found that 1024 bytes gave the best performance while using a very modest 7% of a Xilinx XC4VFX60's slices and only four (of the 232) BRAM blocks available.

Ashwin A. Mendon

Andrew G. Schmidt

Ron Sass

A Hardware Filesystem Implementation with Multidisk Support

This paper presents optimized implementations of two different pipeline FFT processors on Xilinx Spartan-3 and Virtex-4 FPGAs. Different optimization techniques and rounding schemes were explored. The implementation results achieved better performance with lower resource usage than prior art. The 16-bit 1024-point FFT with the R22SDF architecture had a maximum clock frequency of 95.2 MHz and used 2802 slices on the Spartan-3, a throughput per area ratio of 0.034 Msamples/s/slice. The R4SDC architecture ran at 123.8&#x2009;MHz and used 4409 slices on the Spartan-3, a throughput per area ratio of 0.028 Msamples/s/slice. On Virtex-4, the 16-bit 1024-point R22SDF architecture ran at 235.6 MHz and used 2256 slice, giving a 0.104 Msamples/s/slice ratio; the 16-bit 1024-point R4SDC architecture ran at 219.2&#x2009;MHz and used 3064 slices, giving a 0.072 Msamples/s/slice ratio. The R22SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme. This paper also shows that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors.

Bin Zhou

Yingning Peng

David Hwang

Pipeline FFT Architectures Optimized for FPGAs

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International Journal of Reconfigurable Computing

Selected Papers from ReConFig 2008

Selected Papers from ReConFig 2008

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