Hardware-Efficient Design of Real-Time Profile Shape Matching Stereo Vision Algorithm on FPGA
Table 1
Published FPGA implementation of stereo vision algorithms. FPGA resource usage is given, for those publications that provide it, in terms of percentage of configurable logic (%L) and percentage of memory (%M) for the specific device. The one exception is the BP implementation by Pérez et al. [28] which required a device with access to a total of 1.5 GB of memory.