Research Article
Robotic Mapping and Localization with Real-Time Dense Stereo on Reconfigurable Hardware
Table 3
Performance comparison between hardware stereo matching systems.
| Reference | Method of correspondence | Area utilization/memory bits | Image resolution/max disparity | Performance | Quality assessment (average bad matches) | Technology |
| Present work | Dynamic programming/maximum likelihood | 27220 logic elements/413632 | 640 × 480/49 pixels | 25 Mpps/81 fps | <10% | Altera Cyclone II FPGA board + Nios II controller | Diaz et al. (2007) [17] | Phase-based | 13048 slices/1308672 | 1280 × 960/29 pixels | 65 Mpps/52 fps | — | Custom FPGA, Xilinx Virtex-II | Ambrosch et al. (2009) [18] | Correlation-SAD | 106658 logic elements/425984 | 330 × 375/120 pixels | 136 fps | ~38% | FPGA, Altera Stratix EP2S130 | Darabiha et al. (2003) [19] | Local weighted phase correlation | ~67000 4-input LUT/800000 | 360 × 276/20 pixels | 2.8 Mpps/30 fps | <10% | Custom FPGA board Xilinx Virtex 2000 | Liang et al. (2009) [20] | Tile-based belief propagation | 2.5 Mgates total | 640 × 480/64 pixels | 8.2 Mpps/27 fps | — | ASIC | Niitsuma and Maruyama (2004) [21] | Correlation-SAD | 31000 slices/405504 | 640 × 480/27 pixels | 9.2 Mpps/30 fps | — | Custom FPGA Xilinx Virtex-II | Kalomiros and Lygouras (2008) [22] | Correlation-SAD | 15000 logic elements/196000 | 320 × 240/32 pixels | 25 Mpps/325 fps | ~26% | FPGA, Altera Cyclone II | Wang et al. (2006) [23] | Dynamic programming | — | 640 × 480/48 pixels | 1 Mpps/3 fps | <10% | Graphics processing unit |
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