Research Article
Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm
Table 5
Experimental results for stage 1.
| | | Slices | Slice FF | 4-input LUT | FIFO16/ RAMB1 | (ms) | (ms) | Speedup |
| | 8 | 32 | 1651 (1.85%) | 1908 (1.07%) | 3047 (1.71%) | 25 (7.44%) | 0.04 | 1.27 | 29.59× | | 9 | 64 | 3011 (3.38%) | 3596 (2.02%) | 5515 (3.1%) | 27 (8.04%) | 0.19 | 2.64 | 13.87× | | 10 | 128 | 5860 (6.58%) | 7201 (4.04%) | 11186 (6.28%) | 33 (9.82%) | 0.49 | 7.22 | 14.78× | | 11 | 128 | 6191 (6.95%) | 7728 (4.34%) | 11755 (6.60%) | 43 (12.80%) | 1.01 | 22.97 | 22.74× | | 12 | 256 | 11880 (13.34%) | 14907 (8.37%) | 22573 (12.67%) | 55 (16.37%) | 2.54 | 82.28 | 32.46× | | 13 | 256 | 14101 (15.83%) | 16981 (9.53%) | 25676 (14.41%) | 95 (28.27%) | 8.89 | 596.9 | 67.13× |
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esource percentages are for a Virtex-4 XC4VLX200ff1513-11.
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