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IET Circuits, Devices & Systems
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IET Circuits, Devices & Systems
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2023
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Article
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Fig 6
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Research Article
A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device
Figure 6
Key process schematic for mini-LOCOS field plate: (a) Step (4); (b) Step (6).
(a)
(b)